Current microprocessor designs need to centralize data transfer operations under control of integrated functional units known as data transfer access units or enhanced direct memory access (EDMA) units. EDMA is of most interest here and specifically of interest are EDMA designs employing hub-and-port style architecture. Such EDMAs feature a hub unit, which maintains a queue of transfer requests and provides priority protocol and proper interfacing for the handling of a large number of such requests. Secondly hub-and-port EDMAs have one or more hub interface units (HIU), which each provide a seamless interface between the EDMA hub and its ports. Ports are typically external application units (AU) otherwise known as peripheral units. Internal memory ports are also included among the EDMA ports.
FIG. 1 illustrates the essentials of a prior art microprocessor system having EDMA 100 and central processing unit (CPU) 101. EDMA 100 includes transfer controller 102 and hub interface units (HIU) 104, 105, and 106. Communication between the transfer controller hub unit 102 and HIUs 104, 105, and 106 employs buses 103, 107, 108, 109, and 110. Each HIU provides interface to a single port. Peripheral unit 114 and 115 communication with corresponding HIUs 104 and 105 via respective paths 111 and 112. The microprocessor system also includes the internal memory port device 116 which communications with HIU 106 via path 113. The EDMA 100 responds to transfer requests not only from CPU 101 but also from any of the ports it services. Transfer requests (TR) handled by transfer controller (TC) hub unit 102 involve transfer of data from one port to another. Transfer commands reside in transfer request packets that give all the detailed parameters of a transfer.
There are a variety of hub interface units (HIU) designed to have a range of capabilities and performance characteristics. Among these are: (1) synchronous HIU; (2) asynchronous HIU; (3) master HIU; (4) slave HIU; (5) full word 32-Bit HIU; (6) double word 64-Bit HIU; and (7) internal memory port (IMP) which is sometimes referred to as a fast port. An HIU must be designed to provide the most efficient data transfer with maximum bandwidth and minimal latency for the attached port. Providing this variety of HIU needed in various designs increases the scope of design and verification tasks. Clearly, any methodology that simplifies the design of multiple HIUs that reduces design time and simplifies verification is most desirable.